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MC74F543 OCTAL REGISTERED TRANSCEIVER, NON-INVERTING, 3-STATE
The MC74F543 Octal Registered Transceivers contain two sets of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The MC74F543 has a noninverting data path. The A outputs are guaranteed to sink 20 mA while the B outputs are rated for 64 mA.
OCTAL REGISTERED TRANSCEIVER, NON-INVERTING, 3-STATE
FASTTM SCHOTTKY TTL
* * * * * * * * * * *
Combines 74F245 and 74F373 Type Functions in One Chip 8-Bit Octal Transceiver Non-Inverting Back-to-Back Registers for Storage Separate Controls for Data Flow in Each Direction Glitchless Outputs During 3-State Power Up or Power Down Operation High Impedance Outputs in Power Off State A Outputs Sink 24 mA and Source 3.0 mA B Outputs Sink 64 mA and Source 15 mA See F544 for Inverting Version ESD Protection > 4000 Volts PIN ASSIGNMENT
VCC EBA 24 23 B0 22 B1 21 B2 20 B3 19 B4 18 B5 17 B6 16 B7 LEAB OEAB 15 14 13
24 1
N SUFFIX PLASTIC CASE 724-03
24 1
DW SUFFIX SOIC CASE 751E-03
ORDERING INFORMATION
MC74FXXXN Plastic MC74FXXXDW SOIC 1 2 3 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 11 12
LEBA OEBA A0
EAB GND
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 25 Max 5.5 70 - 3.0 / - 15 24 / 64 Unit V C mA mA
FAST AND LS TTL DATA 4-212
MC74F543
FUNCTION TABLE
Inputs OEXX H L L L L L L EXX X H H L L L L LEXX X L L H H L L Data X l h l h L H Outputs Z Z Z L H L H Status Outputs disabled Outputs disabled Data latched Data latched Transparent
H = HIGH voltage level: h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): L = LOW Voltage Level: I = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): X = Don't care: Z = HIGH impedance state.
FUNCTIONAL DESCRIPTION The MC74F543 contains two sets of eight D-type latches, with separate input and controls for each set. For data flow from A to B, for example, the A-to-B Enable (EAB) Input must be LOW in order to enter data from A0 - A7 or take data from B0 - B7, as indicated in the Function Table. With EAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-State B output buffers are active and reflects the data present at the output of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA, and OEBA inputs.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 2.4 A0 - A7 VOH Output HIGH Voltage B0 - B7 A0 - A7 VOL Output LOW Voltage B0 - B7 74 I/O Pins IIH Input HIGH Current Control Pins 20 EAB, EBA IIL Input LOW Current Other Inputs Off-State Output Current, High-Level Voltage Applied Off-State Output Current, Low-Level Voltage Applied Output Short Circuit Current (Note 2) An Outputs Bn Outputs ICCH ICC Total Supply Current ICCL ICCZ - 60 - 100 70 95 95 - 0.6 70 1.0 - 600 -150 mA -225 100 125 125 mA VCC = MAX VCC = MAX, VOUT = 0 V A mA A - 1.2 mA VCC = MAX, VIN = 0.5 V VOUT = 2.7 V VOUT = 5.5 V 0.4 0.55 1.0 100 V mA A 74 74 74 2.7 2.0 0.35 0.5 3.4 V V V IOH = - 3.0 mA IOH = - 15 mA IOL = 24 mA IOL = 64 mA -0.73 Parameter Min 2.0 0.8 - 1.2 Typ Max Unit V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN, IIN = - 18 mA VCC = 4.5 V VCC = 4.75 V VCC = 4.5 V VCC = MIN
VCC = MAX, VIN = 5.5 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 2.7 V
IOZH IOZL IOS
VCC = MAX
VCC = MAX, VOUT = 0.5 V
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA 4-213
MC74F543
AC ELECTRICAL CHARACTERISTICS
74F TA = + 25C VCC = + 5.0 V CL = 50 pF Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay Transparent Mode An to Bn or Bn to An Propagation Delay LEBA to An Propagation Delay LEAB to Bn Output Enable Time to OEBA or OEAB to An or Bn EBA or EAB to An or Bn Output Disable Time to OEBA or OEAB to An or Bn EBA or EAB to An or Bn Min 70 3.0 3.0 4.5 4.5 4.5 4.5 3.0 4.0 2.5 2.0 Typ 100 5.5 5.0 8.5 8.5 8.5 8.5 7.0 7.5 6.0 5.5 7.5 6.5 11 11 11 11 9.0 10.5 8.0 7.5 Max 74F TA = 0C to + 70C VCC = + 5.0 V 10% CL = 50 pF Min 70 3.0 3.0 4.5 4.5 4.5 4.5 3.0 4.0 2.5 2.0 8.5 7.5 12.5 12.5 12.5 12.5 10 12 9.0 8.5 Max Unit MHz ns
ns ns
ns
ns
AC OPERATING REQUIREMENTS
74F TA = + 25C VCC = + 5.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) tw(L) Parameter Setup Time, HIGH or LOW An or Bn to LEBA or LEAB Hold Time, HIGH or LOW An to Bn to LEBA or LEAB Latch Enable, B to A Pulse Width, LOW Min 3.0 3.0 3.0 3.0 8.0 Typ Max 74F TA = 0C to + 70C VCC = + 5.0 V 10% CL = 50 pF Min 3.5 3.5 3.5 3.5 9.0 Typ Max Unit ns ns ns
FAST AND LS TTL DATA 4-214
MC74F543
LOGIC DIAGRAM
DETAIL A
DQ LE A0
B0
QD LE B1 B2 DETAIL A X 7 B3 B4 B5 B6 B7
A1 A2 A3 A4 A5 A6 A7
OEBA OEAB EBA LEBA EAB LEAB
NOTE: Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FAST AND LS TTL DATA 4-215

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